EEL 4768 Computer
Architecture
Department of Electrical and Computer Engineering
University of Central Florida, Fall 2016
Course Information - Description
- Prerequisites - Textbooks
- Syllabus - Organization -
Grading - Schedule, Notes &
Assignments - Outcomes - Acknowledgment
E-mail: murat.yuksel@ucf.edu
Phone: (407) 823-4181
Web
page: www.ece.ucf.edu/~yuksem
Office: HEC 317A
Office
hours:
E-mail: raghav3276@knights.ucf.edu
Phone: (321) 313-8055
Office: HEC 231
Office
hours:
Computer systems performance and evaluation, processor datapath and control, microprogrammed architectures, instruction and arithmetic pipelines, cache and virtual memory, and RISC vs. CISC.
This is a tentative list of topics, subject to modification and reorganization.
Grading (Tentative)
Both grading policy and scale are subject to change.
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• Grading Policy
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• Grading Scale
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Important Note: Re-grading requests can only be made within the first week after the graded assignments/tests are returned to the students.
Schedule (Tentative), Notes & Assignments
This is a tentative schedule including the exam dates. It is subject to readjustment depending on the time we actually spend in class covering the topics. Slides presented in class and assignments will be posted at the WebCourses.
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Date |
Lectures |
Assignments & Notes |
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Tue, Aug 23 |
Lecture 1: Introduction |
H&P, CA: App A & K HW 0 Out HW 1 Out |
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Thu, Aug 25 |
Lecture 2: Instruction Set Principles (1) |
H&P, CA: App A & K |
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Tue, Aug 30 |
Lecture 3: Instruction Set Principles (2) |
H&P, CA: App A & K HW 0 Due |
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Thu, Sep 1 |
Lecture 4: Instruction Set Principles (3) |
H&P, CA: App A & K |
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Tue, Sep 6 |
Lecture 5: Datapath Design – Single-cycle (1) |
H&P, COD: Ch 4 HW 1 Due |
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Thu, Sep 8 |
Lecture 6: Datapath Design – Single-cycle (2) |
H&P, COD: Ch 4 HW 2 Out |
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Tue, Sep 13 |
Lecture 7: Datapath Design – Single-cycle (3) |
H&P, COD: Ch 4 |
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Thu, Sep 15 |
Lecture 8: Datapath Design – Multi-cycle (1) |
H&P, COD: Ch 4 |
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Tue, Sep 20 |
Lecture 9: Datapath Design – Multi-cycle (2) |
H&P, COD: Ch 4 HW 2 Due HW 3 Out |
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Thu, Sep 22 |
Lecture 10: Datapath Design – Multi-cycle (3) |
H&P, COD: Ch 4 |
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Tue, Sep 27 |
Lecture 11: Datapath Design – Multi-cycle (4) |
H&P, COD: Ch 4 HW 4 Out |
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Thu, Sep 29 |
Lecture 12: Datapath Design – Multi-cycle (5) |
H&P, COD: Ch 4 |
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Tue, Oct 4 |
Lecture 13: Datapath Design – Multi-cycle (6) |
H&P, COD: Ch 4 |
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Thu, Oct 6 |
Cancelled due to Hurricane Matthew |
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Tue, Oct 11 |
Midterm Review |
HW 3 Due HW 4 Due HW 5 Out |
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Thu, Oct 13 |
Midterm Exam |
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Tue, Oct 18 |
Lecture 14: Datapath Design – Pipelined (1) |
H&P, COD: Ch 4 |
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Thu, Oct 20 |
Lecture 15: Datapath Design – Pipelined (2) |
H&P, COD: Ch 4 |
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Tue, Oct 25 |
Lecture 16: Datapath Design – Pipelined (3) |
H&P, COD: Ch 4 HW 5 Due HW 6 Out |
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Thu, Oct 27 |
Lecture 17: Datapath Design – Pipelined (4) |
H&P, COD: Ch 4 |
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Tue, Nov 1 |
EduMIPS Examples |
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Thu, Nov 3 |
Lecture 18: Datapath Design – Control Hazards (1) |
H&P, COD: Ch 4 |
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Tue, Nov 8 |
Lecture 19: Datapath Design – Control Hazards (2) |
H&P, COD: Ch 4 |
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Thu, Nov 10 |
Lecture 20: Instruction Level Parallelism (1) |
H&P, CA: Ch 3.1-3.5 HW 6 Due HW 7 Out |
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Tue, Nov 15 |
Lecture 21: Instruction Level Parallelism (2) |
H&P, CA: Ch 3.1-3.5 |
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Thu, Nov 17 |
Lecture 22: Instruction Level Parallelism (3) |
H&P, CA: Ch 3.7, 3.8 |
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Tue, Nov 22 |
Lecture 23: Memory Hierarchy (1) |
H&P, CA: Ch 2.1, 2.4, 2.5 |
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Thu, Nov 24 |
Thanksgiving – NO
CLASS |
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Tue, Nov 29 |
Lecture 24: Memory Hierarchy (2) |
H&P, CA: Ch 2.1, 2.4, 2.5 HW 7 Due |
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Thu, Dec 1 |
Final Review |
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Dec 8, 1-3:50pm |
Final Exam |
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Course Objectives
This course explores intermediate topics in computer architecture. We will start by introducing computer systems performance and evaluation. Next, we will explain the MIPS architecture and assembly language including the 32-bit and 64-bit versions. The hardware implementation of MIPS architecture will also be introduced, including single-cycle, multi-cycle and pipelined datapath. The next topic is the memory of computer where we will describe the cache memory and virtual memory. Then we will explore the topic of parallelism and multi-cores where the computer system uses multiple CPUs and is able to run programs in parallel. Finally, we will focus on the topic of instruction-level parallelism where one CPU is able to run multiple instructions simultaneously.
· The students shall be able to understand register-transfer-level (RTL) design of control and data path.
· The students shall be able to analyze the computer performance such as CPU execution time and average memory access time.
· The students shall understand the fundamental concepts and techniques in computer architecture, including instruction set architecture, pipelining, memory hierarchy and exploitation of instruction-level parallelism.
· The students shall be able to understand the state-of-the-art design and implementation of GPU and emerging memory technologies
The slides and other materials for this course are in part based upon the materials from a number of people/sources, including:
· Official website for the Hennessy & Paterson, Computer Architecture text: Computer Architecture, A Quantitative Approach
· Official website for the Hennessy & Paterson, Computer Organization and Design text: Computer Organization and Design, The Hardware/Software Interface
· Zakhia Abichar from UCF:
http://www.eecs.ucf.edu/~zakhia17
· Deilang Fan from UCF: http://www.eecs.ucf.edu/~dfan
·
Mircea Nicolescu from UNR: https://www.cse.unr.edu/~mircea
·
Michael Leverington from UNR: https://www.cse.unr.edu/~michael
Course Information - Description
- Prerequisites - Textbooks
- Syllabus - Organization -
Grading - Schedule, Notes &
Assignments - Outcomes - Acknowledgment
Last updated on November 11, 2016