{"id":418,"date":"2024-10-18T09:52:18","date_gmt":"2024-10-18T13:52:18","guid":{"rendered":"https:\/\/www.ece.ucf.edu\/labs\/EEL3004\/?page_id=418"},"modified":"2025-03-31T13:48:10","modified_gmt":"2025-03-31T17:48:10","slug":"project-2-time-delay-circuit-design","status":"publish","type":"page","link":"https:\/\/www.ece.ucf.edu\/labs\/EEL3004\/project-2-time-delay-circuit-design\/","title":{"rendered":"Project #2 Time Delay Circuit Design"},"content":{"rendered":"<h3>Objectives<\/h3>\n<p>The ultimate goal of the project is to design a circuit that implements a specific time delay in the process of turning on a light emitting diode (LED).<\/p>\n<h3>Tools<\/h3>\n<ul>\n<li>Circuit Simulator<\/li>\n<li>Lab Equipment<\/li>\n<\/ul>\n<h3>I. Circuit Network<\/h3>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-231 aligncenter size-full\" src=\"https:\/\/www.ece.ucf.edu\/labs\/EEL3004\/wp-content\/uploads\/2024\/10\/Time-Delay.png\" alt=\"\" width=\"642\" height=\"310\" \/><\/p>\n<p style=\"text-align: center;\"><strong>Figure 1\u00a0 \u00a0 \u00a0Circuit Network of Interest<\/strong><\/p>\n<p>As shown in Figure 1, the circuit network considered in this project has three major parts: DC voltage source (Vs), time delay circuit (TDC) and printed circuit board (PCB). The connections required to integrate the three parts are as follows:<\/p>\n<ol>\n<li>Input terminals of TDC are connected to Vs.<\/li>\n<li>Output terminals of TDC are connected to Vin+ and ground (GND) of PCB.<\/li>\n<li>Vin- of PCB is connected to Vref, which is a DC voltage with a specific value.<\/li>\n<li>+10V of PCB is connected to a +10V DC voltage <strong>or<\/strong> GND.<\/li>\n<li>-10V of PCB is connected to a -10V DC voltage <strong>or<\/strong> GND.<\/li>\n<\/ol>\n<p>On the printed circuit board (PCB), there are two LEDs: green and red. The conditions for turning on these two LEDs are as follows:<\/p>\n<ul>\n<li><strong>Green LED:<\/strong>\u00a0 \u00a0Vin+ \u2265 Vin- <strong>and<\/strong> +10V of PCB is connected to a +10V DC voltage<\/li>\n<li><strong>Red LED:<\/strong>\u00a0 \u00a0Vin- \u2265 Vin+ <strong>and<\/strong> -10V of PCB is connected to a -10V DC voltage<\/li>\n<\/ul>\n<h3>II. Network Functionality<\/h3>\n<p>The circuit network in Figure 1 can be used to perform several functions. They include, but not limited to, the following:<\/p>\n<ol>\n<li>turn on the green LED after a specific time delay, t<sub>d<\/sub>, for a given Vref value<\/li>\n<li>turn on the red LED after a specific time delay, t<sub>d<\/sub>, for a given Vref value<\/li>\n<li>turn on both LEDs alternately with specific time intervals<\/li>\n<\/ol>\n<p>For the current project, the focus will be on <strong>Function #1<\/strong>. Students are highly encouraged to work on implementing the remaining functions at their leisure.<\/p>\n<h3>III. The Challenge<\/h3>\n<p>Given the following items:<\/p>\n<ol>\n<li>a PCB with a red LED and a green LED on board<\/li>\n<li>a specified value for Vref<\/li>\n<li>a desired time delay value, t<sub>d<\/sub><\/li>\n<\/ol>\n<p>the challenge is to perform all necessary steps such that the green LED will turn on only after the DC voltage source, Vs, has been turned on for a time duration specified by t<sub>d<\/sub>. A successful challenge completion is demonstrated in the following video.<\/p>\n<div style=\"text-align: center;\"><iframe loading=\"lazy\" src=\"https:\/\/www.ece.ucf.edu\/labs\/EEL3004\/wp-content\/uploads\/2024\/10\/Project-Demo.mp4\" width=\"760\" height=\"315\" frameborder=\"0\" autostart=\"false\" allowfullscreen=\"allowfullscreen\"><\/iframe><\/div>\n<p style=\"text-align: center;\"><strong>Video 1\u00a0 \u00a0 \u00a0A Successful Challenge Completion<\/strong><\/p>\n<p>To successfully tackle the challenge, complete the following tasks.<\/p>\n<ol>\n<li>Design the TDC.<\/li>\n<li>Determine the required value for Vs.<\/li>\n<li>Construct the circuit network in Figure 1 using the provided PCB. In addition to all other required connections, make the following connections:\n<ol style=\"list-style: upper-alpha;\">\n<li>+10V of PCB to a +10V DC voltage<\/li>\n<li>-10V of PCB to GND<\/li>\n<\/ol>\n<\/li>\n<li>Demonstrate to your ULAs that the green LED on the provided PCB can indeed be turned on only after the specified time duration has elapsed.<\/li>\n<li>Perform Step #4 three times and record down all 3 time delays using a timer.<\/li>\n<li>All 3 measured time delay values must fall within \u00b120% of the specified value t<sub>d<\/sub>. You can exclude the adverse effect of human response time.<\/li>\n<\/ol>\n<p><strong>TECHNICAL NOTES:<\/strong><\/p>\n<ul>\n<li><strong>All node voltages, including Vin+, Vin-, +10V, and -10V of PCB, are defined with respect to the ground (GND).<\/strong> You should have this basic principle ingrained in your brain by now&#8230;&#8230;&#8230;<\/li>\n<li><strong>WARNING:<\/strong> Make sure that the input values for both Vin+ and Vin- <strong>DO NOT<\/strong> exceed \u00b112V. Otherwise, circuit components on the PCB could be damaged.<\/li>\n<\/ul>\n<h3>IV. Assessment<\/h3>\n<p>The overall weighted grading scheme is as follows:<\/p>\n<p style=\"text-align: center;\"><strong>Table 1\u00a0 \u00a0 \u00a0Overall Weighted Grading Scheme<\/strong><\/p>\n\n<table id=\"tablepress-2\" class=\"tablepress tablepress-id-2\">\n<thead>\n<tr class=\"row-1\">\n\t<th class=\"column-1\">Category<\/th><th class=\"column-2\">Percent of Overall Grade<\/th>\n<\/tr>\n<\/thead>\n<tbody class=\"row-striping row-hover\">\n<tr class=\"row-2\">\n\t<td class=\"column-1\">Design Analysis (Simulation &amp; Hand Analysis)<\/td><td class=\"column-2\">30%<\/td>\n<\/tr>\n<tr class=\"row-3\">\n\t<td class=\"column-1\">Implementation (No Partial Credit)<\/td><td class=\"column-2\">40%<\/td>\n<\/tr>\n<tr class=\"row-4\">\n\t<td class=\"column-1\">Report<\/td><td class=\"column-2\">30%<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<!-- #tablepress-2 from cache -->\n<p><strong>IMPORTANT NOTES:<\/strong><\/p>\n<ul>\n<li>In the real world, your client will only accept an end product that is fully functional as specified or reject a failed product outright. <strong>Hence, the 40% score for implementation will be awarded based on all-or-nothing basis. To earn the full 40% score, all 3 measured time delay values must fall within \u00b120% of the specified value t<sub>d<\/sub>.<\/strong><\/li>\n<li><strong>DO NOT blindly play around with component values using a circuit simulator in the hope that you will discover a working design. Even if you somehow manage to discover a working design magically, you will still lose substantial points in this project since you won&#8217;t be able to dissect your circuit design in your report using circuit theory, calculations, etc.<\/strong><\/li>\n<li>All project demonstrations must be performed during a lab session. No project demonstration can be performed outside lab session.<\/li>\n<li><strong>HEADS UP:<\/strong> Completing all the required tasks in this project requires substantial effort and time. To prepare fully for your project execution and demonstration, you are highly encouraged to complete the design analysis at home.<\/li>\n<\/ul>\n<h3>V. Report<\/h3>\n<p>Document all your analysis, results and findings in a report. The content of your report should include, but not limited to, the following sections.<\/p>\n<ul>\n<li>Objectives and Tasks\u00a0\u2013 define and outline explicitly the objectives and tasks<\/li>\n<li style=\"text-align: left;\">Dissection of Design \u2013 present your circuit design in a detailed, part-by-part analysis\n<div style=\"white-space: pre;\">                                      \u2013 explain the reasonings behind your circuit design using circuit theory<\/div>\n<div style=\"white-space: pre;\">                                      \u2013 provide detailed circuit analysis and calculation to justify the circuit topology,<\/div>\n<div style=\"white-space: pre;\">                                         component type and component value used in your design<\/div>\n<\/li>\n<li>Simulation Results \u2013 present your simulation results with clarity\n<div style=\"white-space: pre;\">                                  \u2013 include screenshots of simulated circuits, results, etc.<\/div>\n<\/li>\n<li>Experimental Results \u2013 present your experimental results with clarity<\/li>\n<li>Results Comparison \u2013 compare simulation and experimental results\n<div style=\"white-space: pre;\">                                     \u2013 explain discrepancies pertaining to concepts<\/div>\n<\/li>\n<li>Conclusions<\/li>\n<\/ul>\n<p>The weighted grading scheme is as follows:<\/p>\n<p style=\"text-align: center;\"><strong>Table 2\u00a0 \u00a0 \u00a0Weighted Grading Scheme for Report<\/strong><\/p>\n\n<table id=\"tablepress-3\" class=\"tablepress tablepress-id-3\">\n<thead>\n<tr class=\"row-1\">\n\t<th class=\"column-1\">Category<\/th><th class=\"column-2\">Percent of Overall Grade<\/th>\n<\/tr>\n<\/thead>\n<tbody class=\"row-striping row-hover\">\n<tr class=\"row-2\">\n\t<td class=\"column-1\">Objectives and Tasks<\/td><td class=\"column-2\">2.5%<\/td>\n<\/tr>\n<tr class=\"row-3\">\n\t<td class=\"column-1\">Dissection of Design<\/td><td class=\"column-2\">15.0%<\/td>\n<\/tr>\n<tr class=\"row-4\">\n\t<td class=\"column-1\">Simulation Results<\/td><td class=\"column-2\">2.5%<\/td>\n<\/tr>\n<tr class=\"row-5\">\n\t<td class=\"column-1\">Experimental Results<\/td><td class=\"column-2\">2.5%<\/td>\n<\/tr>\n<tr class=\"row-6\">\n\t<td class=\"column-1\">Results Comparison<\/td><td class=\"column-2\">5.0%<\/td>\n<\/tr>\n<tr class=\"row-7\">\n\t<td class=\"column-1\">Conclusions<\/td><td class=\"column-2\">2.5%<\/td>\n<\/tr>\n<tr class=\"row-8\">\n\t<td class=\"column-1\">Total<\/td><td class=\"column-2\">30%<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<!-- #tablepress-3 from cache -->\n","protected":false},"excerpt":{"rendered":"<p>Objectives The ultimate goal of the project is to design a circuit that implements a specific time delay in the &hellip; <a href=\"https:\/\/www.ece.ucf.edu\/labs\/EEL3004\/project-2-time-delay-circuit-design\/\" class=\"more-link\">Continue reading <span class=\"screen-reader-text\">Project #2 Time Delay Circuit Design<\/span><\/a><\/p>\n","protected":false},"author":3,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-418","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/www.ece.ucf.edu\/labs\/EEL3004\/wp-json\/wp\/v2\/pages\/418","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.ece.ucf.edu\/labs\/EEL3004\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.ece.ucf.edu\/labs\/EEL3004\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.ece.ucf.edu\/labs\/EEL3004\/wp-json\/wp\/v2\/users\/3"}],"replies":[{"embeddable":true,"href":"https:\/\/www.ece.ucf.edu\/labs\/EEL3004\/wp-json\/wp\/v2\/comments?post=418"}],"version-history":[{"count":75,"href":"https:\/\/www.ece.ucf.edu\/labs\/EEL3004\/wp-json\/wp\/v2\/pages\/418\/revisions"}],"predecessor-version":[{"id":516,"href":"https:\/\/www.ece.ucf.edu\/labs\/EEL3004\/wp-json\/wp\/v2\/pages\/418\/revisions\/516"}],"wp:attachment":[{"href":"https:\/\/www.ece.ucf.edu\/labs\/EEL3004\/wp-json\/wp\/v2\/media?parent=418"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}