% !TEX root = master.tex
\subsubsection{MSP430F6659}

\begin{table}[!ht]
	\centering
	\caption[MSP430F6659 Basic Specifications]{MSP430F6659 Basic Specifications \cite{MSP430F6659}}
	\label{tab:msp430f6659}
	\begin{tabularx}{\textwidth}{|X|X|X|}
		\hline
		\textbf{Specification} & \textbf{Value} & \textbf{Summary of Interest}\\ 
		\hline\hline 
		Main Clock Speed & 20MHZ & Max base clock, is a adequate speed \\ 
		\hline 
		Primary Storage & 64KB & A large amount to work with, will potentially help quite abit with buffer streaming \\ 
		\hline 
		Secondary Storage & 512KB  & Allows a large potential in look-ups and more advanced code to speed up code \\ 
		\hline 
		Communication Module & 3 USCI, USB & Adds a large improvement to communication control and offloading  \\
		\hline
		Clock System & Watch Crystal, Internal Programmable, External Crystal, FLL & More advanced clock system, adds in the ability for over-clocking by usage of external crystals and/or FLL usage \\ 
		\hline 
		Additional Modules & Hardware Multiplier, DMA, DAC & Options to help offload computations, and potentially useful digital to analog conversion software \\ 
		\hline 
	\end{tabularx} 
\end{table}

The MSP430F6659 is another device that was considered underneath the MSP430 line. The main considerations with this device were mostly performance related, due to the failure of the earlier devices. The main objects of interest were its slightly different clock system, the three USCI modules, the amount of flash plus ram available, and the inclusion of the MPY, DMA, and various other useful hardware modules.

The clock system capabilities were of key interest to system design. The clock capabilities are on par with previous mentioned microcontrollers, but the main focus on how to truly unlock the microcontroller's capability. The frequency locked loop used in the clock control is key to 
overclocking the system. Overclocking is fundamentally just running the system at a higher clock, this technique would have hopefully sidestepped an issue that was ran into earlier in testing. The overhead for sending data with the display system at the time was a massive percentage of the total CPU time available. Thus the idea for overclocking the system was investigated and deemed feasible with the implementation of the F6659 microcontroller. By adjusting the FLL outside the stable bounds it was predicted to be able to obtain a 50 percent increase in clock speed over the base max stable. Additionally to add to the total temptation of swapping to this device was its massive 512KB flash and 64KB ram which was a jump forward from the MSP430FR6989. This would open up a multitude of possible implementations of the software as more room was available to act as buffer. On-top of these previous notable improvements was the inclusion of multiple USCI modules which also opened a multitude of additional implementation ideas and also solved the issue of only having one bus for multiple devices using different protocols. And finally, all the previous mentioned hardware modules are included in the package, thus keeping possible implementations and optimizations freely available to squeeze out the maximum amount of efficient cycle usage.

In conclusion to this device consideration, the device was potentially powerful enough to handle the requested feature set for the Smart Table. Though, the main issues were the proposed instability of going outside of the given stable frequencies and thus relying on silicon lottery to keep the project flowing. Additionally even with this speed increase, some of the proposed software modules would have pushed the total cycle costs to the limit of whats available. Therefore this microcontroller is listed as a backup device for development if any events happen that pause production in the final microcontroller choice. \cite{MSP430F6659}
