% !TEX root = master.tex
\subsubsection{TMS320F28379D}

\begin{table}[!ht]
	\centering
	\caption[TMS320F28379D Basic Specifications]{TMS320F28379D Basic Specifications \cite{TMS320F28379D}}
	\label{tab:tms320f28379d}
	\begin{tabularx}{\textwidth}{|X|X|X|}
		\hline
		\textbf{Specification} & \textbf{Value} & \textbf{Summary of Interest}\\ 
		\hline\hline 
		Main Clock Speed & 200MHZ & Massively powerful, will allow the additional features that are highly computationally expensive \\ 
		\hline 
		Primary Storage & 164KB & A copiously sized working space for the expensive code implementation \\ 
		\hline 
		Secondary Storage & 1024KB  & This allows for a large amount of optimizations in code, with the ability to hardcode in look-up tables \\ 
		\hline 
		Communication Module & 4 USB, uPP, CAN, SPI, SCI/UART, I2C & Covers every possible issues pertaining to communications  \\
		\hline
		Clock System & Unified System & High accuracy and moderately flexible system \\ 
		\hline 
		Additional Modules & FPU, TMU, CLA, ADC, DAC & Large amount of hardware for offloading processes \\ 
		\hline 
	\end{tabularx} 
\end{table}
This microcontroller's basic specifications of 200MHZ clock speed, 1024KB of flash storage, and 164KB SRAM already set it apart from the competition. In addition to the base speeds it must be noted that this device has the D designation implying that the device is of the dual-core type. As the device is a dual core, each core runs independently from the other at the full rated speeds (200MHZ) and contains each an independent memory and ram allocation with a shared buffer between the two for communications. This hardware design leads to the implementation of a real-time operating system with partial threading support which will be highly useful for the Smart Table implementation as the feature-set is a computationally expensive and costly set of features to implement on a single microcontroller. Additionally the microcontroller includes many other features which make it a very enticing microcontroller for implementation as the core for the project.

On-board this microcontroller are a number of useful and interesting hardware modules for various uses. The easiest and mostly immediately recognizable modules to examine are the communication interfaces that are included in the package. As this microcontroller is a much more advanced device compared to more conventional ones, the communications implemented are additionally more advanced; as such the included communication modules are capable of handling USB 2.0, uPP, CAN, SPI, McBSPs, SCI/UART, and I2C which essentially covers every possible basic communication protocol needed. The more uncommon modules included on this unit include; control law accelerators, floating point units, trigonometric math unit, and a Viterbi math unit. Each one of this modules are exceedingly useful and interesting in the offered functionality. The control law accelerators are a different take on offloading floating point instructions, this units are essentially floating point units with independent instruction pipelines and datapaths which run concurrently and parallel to the main CPU while additionally being clocked at the same speed and controlled by interrupts. This offers the ability to offload a number of instructions without any sort of cycle stealing and without any intervention of the main CPU which is exceedingly useful in any peripherals that need heavy processing but the additional main CPU load would be undesirable behavior. The TMS320F28379D additionally comes with a directly mapped floating point unit additionally to the CLAs. This allows further refinement in computation speeds depending on the application. The Trigonometric math unit (TMU) and the Viterbi/complex math unit (VCU-II) are another two very useful modules integrated with direct access from software. The TMU offers higher performance in applications in which odd signals need to be processed such as phase and magnitude in power applications or FFT algorithms. The Viterbi unit additionally expands the signal processing capabilities by allowing for the implementation of the Viterbi butterfly algorithm which is an useful process in modern digital communications for error estimations at the least. Additionally the instruction sets it adds allow for further FFT refinement which is an implementation that is included in the Smart Table stretch goals. The microcontroller also does offer the standard ADC and PWM controls and various other analog related capabilities as such is required in a normal microcontroller design. 

The main concern with this microcontroller implementation is race conditions resulting from the implementation of threading to control the access to each individual core and to guarantee the proper distribution of clock cycles without having to resort to imprecise clock counting or other methods used in flow control. Another issue arising with the implementation of this microcontroller is the sheer number of pins to be dealt with in the board design, though this is a more minor detail, it still affects final implementation of the device. Overall those concerns are far outweighed by the benefits this microcontroller brings to the table, as the sheer amount of power required for clean implementations of the features to be included in the Smart Table are quite costly and the design team would prefer not offloading the processing and control to another device such as a computer or microcomputer like the raspberry pi. As such this microcontroller hits the requirements set out by the internal design team for implementation of all possible features and stretch features in a small package. \cite{TMS320F28379D}