% !TEX root = master.tex
\subsubsection{MSP430FR6989}

\begin{table}[!ht]
	\centering
	\caption[MSP430FR6989 Basic Specifications]{MSP430FR6989 Basic Specifications \cite{MSP430FR6989}}
	\label{tab:msp430fr6989}
	\begin{tabularx}{\textwidth}{|X|X|X|}
		\hline
		\textbf{Specification} & \textbf{Value} & \textbf{Summary of Interest}\\ 
		\hline\hline 
		Main Clock Speed & 16MHZ & Basic modern speed, average \\ 
		\hline 
		Primary Storage & 2KB & SRAM, then the FRAM additionally acts as Primary  \\ 
		\hline 
		Secondary Storage & 128KB  & FRAM storage, offers potentially higher READ/WRITE times \\ 
		\hline 
		Communication Module & eUSCI & Improved USCI module, essentially adds finer control \\
		\hline
		Clock System & Watch Crystal, Internal Programmable & Standard clock control, watch crystals are always useful \\ 
		\hline 
		Additional Modules & Hardware Multiplier, DMA & Multiplication and memory access are computationally expensive, will help offload cost \\ 
		\hline 
	\end{tabularx} 
\end{table}

The MSP430FR6989 microcontroller is part of the FRAM line of microcontrollers that TI offers. As with the msp430 based microcontrollers, the key points are low power, and quick response times. This particular device was chosen for possible implementation due to the amount of non-volatile memory it had on offering, a large 128KB of storage integrated into the chip. This amount would give plenty of working room for programming, as the minimum storage for a singular frame costs 13KB in the 512 LED implementation that was being discussed at the time. Therefore these chips were further investigated for feasibility of integration into the final product design. Additionally offered by the microcontroller that further made it unique are; a 32-bit hardware multiplier (MPY), three-channel internal direct memory access (DMA), a total of five timer modules with multiple capture/compare registers, 128-bit AES security encryption and decryption processor which is quite useful from random procedural generation, and a enhanced serial communication interface module (eUSCI). 

This device's main selling point is its inclusion of FRAM. As such with any newer technology there are a list of pros and cons with the usage of it that must be especially investigated due to its fledgling status. Some of the advantages it provides are: data reliability, low power, speed, unified memory. Additionally due to it being a part of the msp430 line and TI's support, code can be easily ported over to the newer setup with only minor effort. Data reliability is an extremely interesting point, due to the structure of the cells, the data is almost completely unaffected by stray electric fields and radiation and on-top of that the cells have far greater read-write endurance than flash or EEPROM. As a consequence to the technology, the cells are also low power, without the requirement of charge pumps and/or higher voltages of comparable technology. Speed also is improved in this technology, with a far superior write time versus flash and EEPROM, and an additional compressed write + read/verify ability. Another interesting point of this technology and device integration is its unified memory interface, in which both the standard nonvolatile and volatile memory separation doesn't exist and instead they are one and the same. This leads to an even easier time when designing code and as such the programmer only has to keep in mind overall memory usage instead of two different sections and their usage. As a final addition to top off these bonuses for using a TI FRAM device is the ease of integration into an existing project; C code is completely portable from another msp device with only minor work needed. Even with the entirely different memory structure, the programmer doesn't have to bother with worrying about the differences to re-implement their code. Though of course there are things to pay for with such a technology, such as higher cost of production and lower memory density than comparable technologies.

The direct memory access module also comes integrated cleanly into this package. It provides a high speed and low cost method for moving predefined chunks of data with various methods. The most commonly used purpose of this module is for automatic pulling and moving data between peripherals with a minimum of cpu cost. As this module runs in parallel to the main CPU, it doesn't pull any of the limited cycles for processing. The only considerations the programmer must give to the device is the standard race condition issue in which concurrent access to set resources happens in the wrong order. Another cycle saving hardware module is the hardware multipler; following is a basic implementation in pseudocode of a multiplication operation, multiplication is not an intrinsic low level operation in many microcontrollers. 

 \begin{figure}[!htb]
	\centering
	\includegraphics[width=0.5\linewidth]{img/flowchartpoop/multiplicationasm}
	\caption[ASM Multiplication]{Flow of multiplication in software, in asm}
	\label{fig:MultiASM}
\end{figure}

As it is easy to surmise from \ref{fig:MultiASM}, multiplication is a costly operation, and takes up copious amounts of CPU time when implemented in software. This hardware implementation offered by the MPY allows for an hardware offloading and thus increases speeds up to 17 times versus the software implementation. The module is accessed by predefined macros and is relatively easy to implement. A main draw to using the MSP430FR6989 in relation to this particular module is the possibility of implementing computationally expensive FFT which is a stretch goal for the Smart Table.   

The timer module has previously been expanded upon but the main difference with this devices implementation of the module, is its inclusion of five modules with multiple registers for each. This opens the possibility of multiple parallel lines being driven with proper hardware generated PWM without resorting to bit banging. This is a core issue in the Smart Table project, as display driving is an issue requiring copious optimizations. The security module included with the device also adds a useful ability, of generating an rng number with hardware which provides an optimization for procedural image generation to be also used in the display driving. Finally the eUSCI module is provided with this device. This offers to the project higher bit rates, better interrupt control, and better I2C implementation; all of which are potentially needed depending on the display control style taken and optimizations needed for driving.

Overall this device offered a multitude of improvements over the value line device previously chosen. The additional hardware modules especially offered significant clock optimizations needed for driving. Ultimately this device was passed up due to its hardware limitations imposed upon the FRAM memory. The memory controller is limited to a max speed of 8MHz and as the project requires copious amounts of read/writes this limitation would essentially cause the entire microcontroller to only be able to send display data and never process and of the procedural content or even access peripherals. Thus the memory controller was the main cause of abandonment. \cite{MSP430FR6989}