Our Project Goal
SCALER addresses the critical need for secure hardware by creating a custom extension for the open-source Ibex RISC-V processor designed to mitigate timing and power-based side-channel attacks.
Utilizing the Cadence EDA tool suite, the team is executing a full-flow industrial ASIC design process, from RTL verification and synthesis to physical floorplanning and routing, to transform a side-channel-aware microarchitecture into a design suitable for fabrication. This project not only aims to produce a security-hardened core capable of defending against leakage but also seeks to strengthen the undergraduate talent pipeline by demonstrating a complete RTL-to-GDSII workflow.
The Team
Review Committee & Sponsors
University of Central Florida
- Dr. Chung Yong Chan - Advisor/Professor ECE
- Dr. Mike Borowczak - Advisor/Professor ECE
Northrop Grumman Corporation (Sponsor)
- Brian McNulty - Program Sponsor
- Steve Leonard - Program Manager
- Marlon J. Fuentes - Principal Investigator
- Aaron Lingerfelt - Technical Lead
- Alberto Reategui - Technical Lead
Project Files & Videos
Reports & Documents
- Divide & Conquer Report
- Midterm Milestone Report (First Draft)
- Midterm Milestone Report (Revised)
- SD1 Final Report
- 8-Page Conference Paper
- SD2 Final Report
- CDR Presentation Slides
- Final Presentation Slides
- Final Demo Slides
Demo & Presentation Videos
- Senior Design 1 Demo Video (Mini Demo)
- CDR Presentation Video
- SD2 Midterm Demo Video (Revised)
- Final Presentation Video
- Final Demonstration Video