{"id":94,"date":"2023-11-06T00:00:22","date_gmt":"2023-11-06T05:00:22","guid":{"rendered":"https:\/\/www.ece.ucf.edu\/~kamali\/?page_id=94"},"modified":"2025-09-27T10:12:37","modified_gmt":"2025-09-27T14:12:37","slug":"research","status":"publish","type":"page","link":"https:\/\/www.ece.ucf.edu\/~kamali\/research\/","title":{"rendered":"Research"},"content":{"rendered":"\n

HAVEN Research Group<\/h3>\n\n\n\n
\n
\n
\"\"<\/a><\/figure>\n<\/div><\/div>\n<\/div>\n\n\n\n
\n\n\n\n

Research Projects’ Sponsors <\/h3>\n\n\n\n
\n
\n
\"\"<\/figure>\n<\/div><\/div>\n\n\n\n
\n
\"\"<\/figure>\n<\/div><\/div>\n\n\n\n
\n
\"\"<\/figure>\n<\/div>\n\n\n\n
\n
\"\"<\/figure>\n<\/div>\n\n\n\n
\n
\"\"<\/figure>\n<\/div><\/div>\n\n\n\n
\n
\"\"<\/figure>\n<\/div>\n<\/div>\n\n\n\n
\n
\n
\"\"<\/figure>\n<\/div>\n\n\n\n
<\/div>\n\n\n\n
<\/div>\n\n\n\n
<\/div>\n<\/div>\n\n\n\n
\n\n\n\n

Current Focus of Research (Ongoing)<\/h3>\n\n\n\n

[Research Project 3]
Evolutionary Large Language Models for Hardware Security<\/h4>\n\n\n\n

This research explores the transformative role of Large Language Models (LLMs) in enhancing hardware security throughout the design lifecycle. By leveraging prompt engineering and fine-tuning, LLMs can improve hardware reliability, automate functional and security verification, and detect vulnerabilities early in the design phase\u2014mitigating costly post-fabrication risks. Additionally, this work investigates LLM-driven automation in the IC supply chain, from secure RTL design<\/strong> to synthesis and physical design flows<\/strong>, ensuring robust protection against emerging threats<\/strong> while maintaining system confidentiality, integrity, and availability (CIA triad).<\/p>\n\n\n\n

\"\"<\/figure>\n\n\n\n

Selected Publications:<\/strong><\/p>\n\n\n\n

\n
Paper #1: IEEE ASP-DAC 2025<\/a><\/div>\n\n\n\n
Paper #2: ACM GLSVLSI 2024<\/a><\/div>\n\n\n\n
Paper #3: IEEE ISVLSI 2024<\/a><\/div>\n<\/div>\n\n\n\n
\n\n\n\n

[Research Project 2]
Advancing System Security Solutions for Heterogeneous Integration <\/h4>\n\n\n\n

As Moore\u2019s Law slows and Dennard scaling faces challenges, the semiconductor industry is shifting towards advanced packaging and heterogeneous integration (HI) as the next technological frontier. This research investigates the Security of Heterogeneous Integration (SHI)<\/strong> by extending proven security solutions from 2D SoCs to HI-based System-in-Package (SiP)<\/strong> architectures. We explore trust validation and attack mitigation strategies across the SiP supply chain, addressing emerging security concerns such as fault injection, secure activation and locking, and rule-based security verification<\/strong>. Our work aligns with the NIST MAPT Roadmap and SRC\u2019s Decadal Plan, contributing to the development of end-to-end secure heterogeneous integration<\/strong> for the future of microelectronics.<\/p>\n\n\n

\n
\"\"\n\t\t\t\n\t\t\t\t\n\t\t\t<\/svg>\n\t\t<\/button><\/figure>\n<\/div>\n\n\n

Selected Publications:<\/strong><\/p>\n\n\n\n

\n
Paper #1: IEEE Access 2024<\/a><\/div>\n\n\n\n
Paper #2: ACM DAC 2024<\/a><\/div>\n\n\n\n
Paper #3: IEEE D&T 2023<\/a><\/div>\n<\/div>\n\n\n\n
\n\n\n\n

[Research Project 1]
IC\/IP Protection: Advanced Logic Locking and Secure Activation<\/h4>\n\n\n\n

With the increasing complexity and globalization of the IC supply chain<\/strong>, design teams must collaborate with multiple third parties, often in untrusted environments. This exposes hardware security threats<\/strong> such as IP piracy and IC overproduction<\/strong>. Logic locking is a promising countermeasure that enables designers to safeguard designs throughout the supply chain while allowing post-manufacturing activation. This research focuses on: (1) developing robust locking mechanisms<\/strong>, (2) ensuring secure activation without secret leakage<\/strong>, (3) enhancing resilience against evolving attack models<\/strong>, and (4) adapting logic locking for emerging technologies and new fabrication environments<\/strong>. Additionally, we assess the EDA compatibility and commercialization potential<\/strong> of advanced locking solutions, ensuring practical deployment in modern semiconductor workflows.<\/p>\n\n\n\n

\"\"\n\t\t\t\n\t\t\t\t\n\t\t\t<\/svg>\n\t\t<\/button><\/figure>\n\n\n\n

Selected Publications:<\/strong><\/p>\n\n\n\n

\n
Paper #1: DATE 2023<\/a><\/div>\n\n\n\n
Paper #2: DATE 2023<\/a><\/div>\n\n\n\n
Paper #3: ICCAD 2021<\/a><\/div>\n\n\n\n
Paper #4: DAC 2019<\/a><\/div>\n<\/div>\n\n\n\n
<\/div>\n\n\n\n

Previous\/Other Focus of Research (Previous)<\/h3>\n\n\n\n

[Research Project 4]
Security by Construction: Early Stage Security-aware IC Design and Implementation<\/h4>\n\n\n\n

The shift towards high-level synthesis (HLS)<\/strong> for SoC design<\/strong> enables faster development, reduced verification efforts, and lower costs. However, security concerns such as information leakage and side-channel vulnerabilities<\/strong> can be inadvertently introduced during the HLS translation process. This research establishes early-stage security-aware design methodologies<\/strong>, integrating secure design rule checking<\/strong> at the high-level description (C\/C++). By leveraging techniques such as information flow tracking, path decoupling, and security-aware resource utilization<\/strong>, we aim to embed security constraints<\/strong> early in the IC design lifecycle\u2014ensuring robustness against emerging threats before RTL and gate-level synthesis.<\/p>\n\n\n\n

\"\"\n\t\t\t\n\t\t\t\t\n\t\t\t<\/svg>\n\t\t<\/button><\/figure>\n\n\n\n

Selected Publications:<\/strong><\/p>\n\n\n\n

\n
Paper #1: ASP-DAC 2023<\/a><\/div>\n\n\n\n
Paper #2: IEEE TCAD 2022<\/a><\/div>\n<\/div>\n\n\n\n
\n\n\n\n

[Research Project 3]
Forward Trust in IC Supply Chain: Enabling Secure Authentication and Provisioning <\/h4>\n\n\n\n

This research establishes forward trust<\/strong> by integrating secure authentication and provisioning<\/strong> throughout the IC lifecycle. We focus on: (1) Secure Design for Testability<\/strong>, safeguarding scan chains during testing, (2) Forward Implication<\/strong>, ensuring security at every stage of the supply chain, (3) Secure Communication via Primitives<\/strong>, implementing authenticated encryption for remote activation<\/strong> in 3D designs and IoT applications, and (4) Uniqueness for Activation<\/strong>, creating tamper-resistant activation mechanisms against hammering attacks<\/strong>. By fortifying each step of the IC supply chain, this work builds a comprehensive security framework<\/strong>, mitigating threats from reverse engineering to probing, and ensuring trust in next-generation semiconductor technologies.<\/p>\n\n\n\n

\"\"<\/figure>\n\n\n\n

Selected Publications:<\/strong><\/p>\n\n\n\n

\n
Paper #4: IEEE Access 2024<\/a><\/div>\n\n\n\n
Paper #3: IEEE Access 2021<\/a><\/div>\n\n\n\n
Paper #2: IEEE DCAS 2020<\/a><\/div>\n\n\n\n
Paper #1: RAID 2019<\/a><\/div>\n<\/div>\n\n\n\n
\n\n\n\n

[Research Project 2]
Towards Low Power Interconnection Architectures: Network-on-Chip Optimization<\/h4>\n\n\n\n

As Network-on-Chip (NoC)<\/strong> architectures become the backbone of modern multi-core and many-core processors<\/strong>, optimizing their power efficiency<\/strong> is crucial for sustainable high-performance computing. This research focuses on minimizing static power consumption<\/strong> by addressing inefficiencies in NoC router micro-architectures<\/strong>. By leveraging power-gating techniques<\/strong>, we develop deterministic routing algorithms<\/strong> that strategically reduce packet encounters with power-gated routers, maximizing router idleness and energy savings. Additionally, we optimize routing tables<\/strong> to establish dedicated communication paths, ensuring efficient router utilization. These advancements significantly lower leakage power, reduce latency, and improve overall energy efficiency<\/strong>, making NoC architectures more scalable, cost-effective, and practical for next-generation computing systems<\/strong>.<\/p>\n\n\n\n

\"\"\n\t\t\t\n\t\t\t\t\n\t\t\t<\/svg>\n\t\t<\/button><\/figure>\n\n\n\n
\n
Paper #1: ISLPED 2019<\/a><\/div>\n\n\n\n
Paper #2: ISLPED 2018<\/a><\/div>\n\n\n\n
Paper #3: NOCS 2017<\/a><\/div>\n<\/div>\n\n\n\n
\n\n\n\n
[Research Project 1]
FPGA-based Computer Architecture (Interconnection) Acceleration Solutions<\/h5>\n\n\n\n

FPGA-based acceleration is revolutionizing computer architecture, offering high-performance solutions for algorithm acceleration, AI\/ML processing, cryptography, and networking. This research focuses on FPGA-based NoC simulation and emulation<\/strong>, addressing the critical need for cycle-accurate, high-performance, and flexible NoC evaluation tools. By leveraging FPGA reconfigurability, we optimize NoC emulation by offloading non-computation-intensive components (e.g., Traffic Generators and Receptors) to software<\/strong> for greater programmability, while retaining computation-heavy processes on FPGA for accelerated execution. This approach enhances emulation performance, improves NoC design optimization, and advances application-specific architectures, contributing to the next generation of high-performance computing and multiprocessor system-on-chip (MPSoC) technologies.<\/p>\n\n\n\n

\n
\"\"\n\t\t\t\n\t\t\t\t\n\t\t\t<\/svg>\n\t\t<\/button><\/figure>\n<\/figure>\n\n\n\n
\n
Paper #1: IEEE TC 2017<\/a><\/div>\n\n\n\n
Paper #2: FPL 2016<\/a><\/div>\n<\/div>\n","protected":false},"excerpt":{"rendered":"HAVEN Research Group Research Projects’ Sponsors Current Focus of Research (Ongoing) [Research Project 3] Evolutionary Large Language Models for Hardware Security This research explores the transformative role of Large Language Models (LLMs) in enhancing hardware security throughout the design lifecycle. By leveraging prompt engineering and fine-tuning, LLMs can improve hardware reliability, automate functional and security…","protected":false},"author":3,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_acf_changed":false,"footnotes":""},"class_list":["post-94","page","type-page","status-publish","hentry"],"acf":[],"_links":{"self":[{"href":"https:\/\/www.ece.ucf.edu\/~kamali\/wp-json\/wp\/v2\/pages\/94","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.ece.ucf.edu\/~kamali\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.ece.ucf.edu\/~kamali\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.ece.ucf.edu\/~kamali\/wp-json\/wp\/v2\/users\/3"}],"replies":[{"embeddable":true,"href":"https:\/\/www.ece.ucf.edu\/~kamali\/wp-json\/wp\/v2\/comments?post=94"}],"version-history":[{"count":70,"href":"https:\/\/www.ece.ucf.edu\/~kamali\/wp-json\/wp\/v2\/pages\/94\/revisions"}],"predecessor-version":[{"id":965,"href":"https:\/\/www.ece.ucf.edu\/~kamali\/wp-json\/wp\/v2\/pages\/94\/revisions\/965"}],"wp:attachment":[{"href":"https:\/\/www.ece.ucf.edu\/~kamali\/wp-json\/wp\/v2\/media?parent=94"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}