UCF Computer Engineering

Overview

In this module you will extract a verilog netlist and use Verilog-XL to perform a digital simulation of your inverter. You may choose to use this type of simulation either before or after you do the layout of a cell. Beforehand, you may want to verify the correct operation of a newly designed schematic. If this circuit is large, the digital simulation may considerably faster than performing a full analog Spectre simulation of the circuit. Again, after layout, very large circuits may be very slow to simulate using Spectre. Once your circuit passes LVS, you can run the digital simulation on your schematic since it is equivalent to your layout.

Running Verilog XL.

Create a new Cell View called inv_vtest of type schematic. We are doing this because we will have to rename some of the pins to get verilog to work properly and we don't want to screw up our original schematic.

Create an instance of you inverter in the new cell. Create 4 inputOutput pins called in, out, vdd! and vss! and connect them to the four terminals of the inverter accordingly.

The '!' marks the pins as global nets and is necessary for Verilog, but not for Spectre. We purposely didn't want the supplies to be global nets in our schematic because I find that having to wire up the supplies in the schematic reminds me as I'm designing the circuit that I need to think about how these wires will be routed in the layout.

Check and save your design. Open Verilog XL by clicking Virtuoso->Tools->Simulation->Verilog XL

You will be prompted for a run directory. You can use the default or enter another directory if you wish. Click OK.

The Virtuoso Verilog Environment will open.

Creating the Netlist

Select Setup->Netlist

This will open the netlist option form. Ensure that the List "netlist these views" contains "functional" and "schematic." Click the 'more' button. Rename the Global Power Net and Global Ground Nets to match the names on your schematic (vdd!, vss!). Click OK.

Select Setup->Record Signals

Select "Design Selections" from drop-down menu. Then on your schematic highlight the wires or pins that you would like to record. Click OK.

Select Stimulus->Verilog

Tell the pop-up to create a new stimulus file for you. Select testfixture.verilog and click ok.

Now we are ready to generate a netlist for our schematic. Click the only button that isn't grayed out, or select simulation->start interactive. This will generate a Verilog netlist. The CIW window will tell you whether this was successful or not.

If it succeeded, click the continue button to run the simulation. This will not do anything particularly useful since you still have the default testfixture.verilog file.

Modifying the Stimulus File

We need to modify the stimulus to include our desired stimuli.

Use a text editor and open the file testfixture.verilog from the run directory. It will contain this:

// Verilog stimulus file.
// Please do not create a module in this file.

// Default verilog stimulus.

initial
begin

io_cdsNet1 = 1'bz;
io_cdsNet0 = 1'bz;
io_in = 1'bz;
io_out = 1'bz;

end

Modify it like this.

// Verilog stimulus file.
// Please do not create a module in this file.

// Default verilog stimulus.

initial
begin

io_cdsNet1 = 1'bz;
io_cdsNet0 = 1'bz;
io_in = 1'bz;
io_out = 1'bz;
#20 io_cdsNet1 = 1'b1;
io_cdsNet0 = 1'b0;

#10 io_in = 1'b1;
#10 io_in = 1'b0;
#10 io_in = 1'b1;
#10 io_in = 1'b0;
#30 io_in = 1'b1;

end

#10 means to wait 10 times the global timestep. 1'b0 means the signal is a single bit and we want to set it to 0.

For more info on Verilog stimulus files see this link.

Save the file and close it.

Running the Simulation

In the Verilog window, select simulation->Start Interactive again. It will ask you if you want to regenerate the netlist. Say no since you haven't changed the schematic. Now click continue and it will run using your new testfixture.verilog. Click view waveforms at the bottom of the toolbar to open the waveform viewer.

Once the Simvision window opens, and sometimes this takes a while (I think it has to do with the network and the licensing but I'm not sure), it should automatically display the outputs that you selected. Check it out.