Technical Program

December 8th, 2020


Xilinx Workshop

Time : [Q&A] 12:00PM - 01:00PM (EST) Tentative
: [LABS] 01:00PM - 05:00PM (EST) Tentative

Topic : Developing HPC accelerators using Xilinx FPGAs

Presenter : Parimal Patel, XUP Senior Systems Engineer

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HLS4ML Workshop

Time : 09:00AM - 12:00PM (EST)

Topic : HLS4ML tutorial: Open-Source Design Automation
of Machine Learning Devices

Presenter : Nhan Tran, FastML Organization

Click here for more information and registration

December 9th, 2020

Keynote Talk

Live Session

Time : Wed, Dec 9th, 2020 at 6:00 PM (EST)

Venue : LIVE -- Zoom Video conference.

Topic : Advanced Co-design of Deep Learning Algorithms and Hardware Accelerators

Presenter : Dr. Deming Chen, Abel Bliss Professor of Engineering, UIUC, USA

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Zoom Meeting Room:

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December 9th, 2020 - December 11th, 2020

Asynchronous Parallel Sessions


Machine Learning, AI and Neural Networks

6 Stefano Ribes, Pedro Trancoso, Ioannis Sourdis and Christos-Savvas Bouganis
"Mapping Multiple LSTM models on FPGAs"

91 Andrew Boutros, Eriko Nurvitadhi, Rui Ma, Sergey Gribok, Zhipeng Zhao, James C. Hoe, Vaughn Betz and Martin Langhammer
"Beyond Peak Performance: Comparing The Real Performance of AI-Optimized FPGAs and GPUs"

104 Zhiqiang Que, Hiroki Nakahara, Hongxiang Fan, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Eriko Nurvitadhi and Wayne Luk
"A Reconfigurable Multithreaded Accelerator for Recurrent Neural Network"

S56 Yasuhiro Nitta and Hideki Takase
"An FPGA Accelerator for Bayesian Network Structure Learning with Iterative Use of Processing Elements"

S59 Yue Li, Wei Cao and Lingli Wang
"A Low-Cost Reconfigurable Nonlinear Core for Embedded DNN Applications"


Convolutional Neural Networks (CNN)

24 Shuanglong Liu and Wayne Luk
"Optimizing Fully Spectral Convolutional Neural Networks on FPGA"

62 Lucian Petrica, Tobias Alonso, Mairin Kroes, Nicholas Fraser, Sorin Cotofana and Michaela Blott
"Memory-Efficient Dataflow Inference Acceleration for Deep CNNs on FPGA"

96 Mathew Hall and Vaughn Betz
"From TensorFlow Graphs to LUTs and Wires: Automated Sparse and Physically Aware CNN Hardware Generation"

S26 Shikha Goel, Rajesh Kedia, Rijurekha Sen and M. Balakrishnan
"INFER: INterFerence-aware Estimation of Runtime for Concurrent CNN Execution on DPUs"

S54 Arish S, Sharad Sinha and Smitha K G
"DASH: Design Automation for Synthesis and Hardware Generation for CNNs"


Placement and Routing

9 Hongxin Kong, Lang Feng, Chunhua Deng, Bo Yuan and Jiang Hu
"How Much Does Regularity Help FPGA Placement?"

81 Mohamed A. Elgammal, Kevin E. Murray and Vaughn Betz
"Learn to Place: FPGA Placement Using Reinforcement Learning and Directed Moves"

97 Behnam Khaleghi, Sahand Salamat and Tajana Rosing
"Revisiting FPGA Routing under Varying Operating Conditions"


Security and Cryptography

12 Andrew Boutros, Mathew Hall, Nicolas Papernot and Vaughn Betz
"Neighbors From Hell: Voltage Attacks Against Deep Learning Accelerators on Multi-Tenant FPGAs"

34 Xiang Li, Peter Stanwicks, Georgios Provelengios, Russell Tessier and Daniel Holcomb
"Jitter-based Adaptive True Random Number Generation for FPGAs in the Cloud"

87 Luke Beckwith and William Diehl
"New Directions for NewHope: Improving Performance of Post-Quantum Cryptography through Algorithm-level Pipelining"


FPGA accelerators in Cloud or Network

78 Gongjin Sun and Sang-Woo Jun
"Bandwidth Efficient Near-Storage Accelerator for High-Dimensional Similarity Search"

86 Alec Lu, Zhenman Fang, Nazanin Farahpour and Lesley Shannon
"CHIP-KNN: A Configurable and High-Performance K-Nearest Neighbors Accelerator on Cloud FPGAs"

16 Niklas Schelten, Fritjof Steinert, Anton Schulte and Benno Stabernack
"A High-Throughput, Resource-Efficient Implementation of the RoCEv2 Remote DMA Protocol for Network-Attached Hardware Accelerators"

S15 Shanquan Tian, Andrew Krzywosz, Ilias Giechaskiel and Jakub Szefer
"Cloud FPGA Security with RO-Based Primitives"

S94 Pouya Haghi, Anqi Guo, Tong Geng, Justin Broaddus, Derek Schafer, Anthony Skjellum and Martin Herbordt
"A Reconfigurable Compute-in-the-Network FPGA Assistant for High-Level Collective Support with Distributed Matrix Multiply Case Study"


FPGA architectures, technology and soft-core processors

69 Johannes Pfau, Maximilian Reuter, Klaus Hofmann and Juergen Becker
"Designing Universal Logic Module FPGA Architectures for Use With Ambipolar Transistor Technology"

99 Kaichuang Shi, Hao Zhou and Lingli Wang
"GIB: A Novel Unidirectional Interconnection Architecture for FPGA"

77 Pepijn de Vos, Michael Kirchhoff and Daniel Ziener
"A Complete Open Source Design Flow for Gowin FPGAs"

S106 Nguyen Dao, Andrew Attwood, Bea Healy and Dirk Koch
"FlexBex: A Framework for RISC-V and Embedded FPGA Hybrids for Reconfigurable Instruction Extensions"


FPGA Design Techniques and Tools

3 Yuanlong Xiao, Syed Tousif Ahmed and Andre DeHon
"Fast linking of separately compiled FPGA blocks without a NoC"

13 Sameh Attia and Vaughn Betz
"StateReveal: Enabling Checkpointing of FPGA Designs with Buried State"

S39 Alex R. Bucknall, Shanker Shreejith and Suhaib A. Fahmy
"Build Automation and Runtime Abstraction for Partial Reconfiguration on Xilinx Zynq Ultrascale+"

S70 Khoa Pham, Dirk Koch, Anuj Vaishnav, Konstantinos Georgopoulos, Pavlos Malakonakis, Aggelos Ioannou and Iakovos Mavroidis
"Partial Reconfiguration for Energy Efficiency and Design Productivity in FPGA-Accelerated Data Centres"

S68 Tiago L. Santos and João M. P. Cardoso
"Automatic Selection and Insertion of HLS Directives via a Source-to-Source Compiler"

S71 Westerley Carvalho, Michael Canesche, Lucas Reis, Frank Sill Torres, Lucas Bragança Silva, Peter Jamieson, José Augusto Nacif and Ricardo Ferreira
"A Design Exploration of Scalable Mesh-based Fully Pipelined Accelerators"

S48 Ce Guo and Wayne Luk
"Quantisation-aware Dimensionality Reduction"


High-Throughput Data Processing and Embedded platforms

S14 Yang Yang, Sanmukh Rao Kuppannagari and Viktor K Prasanna
"A High Throughput Parallel Hash Table Accelerator on HBM-enabled FPGAs"

S32 Sultan Alqahtani, Yiqun Zhu, Xiaolin Meng, Xinhua Wang and Qizhi Shi
"Hardware Implementations with High Throughput, Low-Latency and Low-Area for Matrix Inversion"

S25 Ho-Cheung Ng, Izaak Coleman, Ringo Sw Chu, Man-Chung Yu and Wayne Luk
"Acceleration of Short Read Alignment: Exploration of Speed vs Accuracy with Different Strategies"

S33 Xuzhi Zhang and Russell Tessier
"Service Chaining for Heterogeneous Middleboxes"

11 Christian Lienen, Marco Platzer and Bernhard Rinner
"ReconROS: Flexible Hardware Acceleration for ROS2 Applications"

S49 Haowen Chen, Feiteng Li and Zhuo Zhang
"A Bucket-Stream rBRIEF Extraction Architecture for SLAM Applications on Embedded Platforms"

S61 Johan Peltenburg, Lars T.J. Van Leeuwen, Joost Hoozemans, Jian Fang, Zaid Al-Ars and H. Peter Hofstee
"Battling the CPU Bottleneck in Apache Parquet to Arrow Conversion Using FPGA"



A4 Martin Koppehel and Thilo Pionteck
"Ultra-Low-Latency Video Encoding on Heterogenous Hardware Platforms"

A18 Seyedeh Sharareh Mirzargar, Gaietan Renault, Andrea Guerrieri and Mirjana Stojilovic
"Nonintrusive and Adaptive Monitoring for Locating Voltage Attacks in Virtualized FPGAs"

A35 Hankun Lv, Yuchen Ren, Yunhui Qiu, Wenbo Yin and Lingli Wang
"High Throughput and Low Latency Multi-Version Management Key-Value Storage Accelerator"

A46 Daniel Pinheiro Leal, Midori Sugaya, Hideharu Amano and Takeshi Ohkawa
"Automated Integration of High-Level Synthesis FPGA Modules with ROS2 Systems"

A53 Naoto Soga and Hiroki Nakahara
"Design Method for an LUT Network-Based CNN with a Sparse Local Convolution"

A75 Haoyan Liu, Atiyehsadat Panahi, David Andrews and Alexander Nelson
"An FPGA-based Upper-Limb Rehabilitation Device for Gesture Recognition and Motion Evaluation Using Multi-Task Recurrent Neural Networks"

A80 Danielle Tchuinkou Kwadjo, Joel Mandebi Mbongue and Christophe Bobda
"Performance Exploration on Pre-implemented CNN Hardware Accelerator on FPGA"

A90 Tim Todman, David Thomas and Wayne Luk
"Enhancing performance of event-driven processor networks"

A100 Zhiqiang Que, Daniel Holanda Noronha, Ruizhe Zhao, Xinyu Niu, Steven J.E. Wilton and Wayne Luk
"Towards Overlay-based Rapid In-Circuit Tuning ofDeep Learning Designs"

December 11th, 2020

Virtual Banquet

Live Session

Time : Wed, Dec 11th, 2020 at 6:00 PM (EST)

Venue : LIVE -- Zoom Video conference.

Zoom Meeting Room:

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