Developing HPC accelerators using Xilinx FPGAs
Presenter: Parimal Patel, XUP Senior Systems Engineer
December 8th , 2020
Tentative Schedule in Eastern Time zone:
12:00 PM - 1:00 PM Q&A
1:00 PM - 5:00 PM Labs
This tutorial will introduce the Xilinx Vitis development environment for developing FPGA accelerators for HPC applications. Vitis supports OpenCL, C and C++. RTL design flows are also supported for experienced hardware developers. Each of these flows will be discussed along with the open-source Xilinx Runtime Library and Vitis open-source accelerated libraries.
The latest available cloud and local hardware will be covered including AWS-F1, Nimbix, and the range of Alveo accelerator boards. Topics to be covered:
Xilinx Vitis development framework, design flows, and use cases
AWS, Nimbix, and Alveo boards for FPGA acceleration
Demonstration and hands-on-experience
Vitis development flow
Developing, profiling and optimizing applications for FPGA
Using Xilinx accelerator hardware locally and in the cloud
Short-Bio of Presenter:
Parimal received a Doctor of Philosophy in Electrical and Computer Engineering from the University of Texas at Austin, Texas in 1986.
In 1987 he joined the University of Texas as an Assistant Professor, got promoted to Associate and then to Full Professorships. During his tenure at the university he taught variety of courses including Logic Design, Digital Systems Design, Microcomputer Systems (peripheral interface principles), Embedded Systems Design, VLSI System Design, Computer Architecture, RISC Processor Design, Engineering Workstations, and Advanced HDL modeling.
Parimal has always enjoyed teaching and developing new courses. He started as a contract trainer and then full time employee of Xilinx developing variety of courses for Customer Education department. He joined the Xilinx University Program in April 2007 developing new courses, updating current courses, and delivering XUP workshops worldwide, including High-Level Synthesis, Embedded Systems, Advanced Embedded Systems, DSP Design Flow, DSP Implementation Techniques, Designing with SDSoC, Dynamic Partial Reconfiguration, Python Productivity on Zynq (PYNQ), and Accelerated Cloud Computing on AWS with SDAccel.
Duration and mode of delivery: 3 hours of pre-recorded video to be viewed by the attendees prior to the tutorial, 1 hour of Q&A on the day of the tutorial, followed by labs which will be carried out on AWS. Presenter and additional proctors will be available for next 4 hours. Q&A and labs will be done using Zoom meeting.