s Rickard Ewetz - Publications
Department of Electrical Engineering & Computer Science
Department of Electrical Engineering & Computer Science

Rickard Ewetz


JOURNAL PUBLICATIONS
 
  1. [MICRO'23] M. Chowdhuryy, R. Ewetz , A. Awad , F. Yao, "Understanding and Characterizing Side Channels Exploiting Phase Change Memories", in IEEE MICRO (MICRO), (accepted).
  2. [TCAD'22] S. Thijssen, S. Jha, and R. Ewetz, "COMPACT: Flow-Based Computing on Nanoscale Crossbars with Minimal Semiperimeter and Maximum Dimension", in IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems (TCAD), (accepted).
  3. [TODAES'22] N. Uysal and R. Ewetz, "Synthesis of Clock Networks with a Mode Reconfigurable Topology", in ACM Trans. on Design Automation of Electronic Systems (ACM), 2022
  4. [TCAD'21] N Uysal, B. Zhang, S. Jha, and R. Ewetz, "XMAP: Programming Memristor Crossbars for Analog Matrix-Vector Multiplication: Towards High Precision using Representable Matrices", in IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems (TCAD), 2021.
  5. [PRAI'21] A. Michel and R. Ewetz, "A Survey on the Vulnerability of Deep Neural Networks Against Adversarial Attacks, Progress in Artificial Intelligence (PRAI), 2021.
  6. [TCAD'20] B. Zhang, N Uysal, and R. Ewetz, "Computational Restructuring: Rethinking Image Compression using Resistive Crossbar Arrays", in IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems (TCAD), (accepted). [pdf]
  7. [CAL'19] Vamsee Reddy Kommareddy, Baogang Zhang, Fan Yao, R. Ewetz, and Amro Awad, "Are Crossbar Memories Secure? New Security Vulnerabilities in Crossbar Memories", in IEEE Computer Architecture Letters (CAL), (accepted).
  8. [TCAD'19] B. Zhang, N Uysal, D. Fan, and R. Ewetz, "Handling Stuck-at-fault Defects using Matrix Transformation for Robust Inference of DNNs", in IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems (TCAD), (accepted). [pdf]
  9. [TCAD'18] R. Ewetz and C-K. Koh, "Scalable Construction of Clock Trees with Useful Skew and High Timing Quality", in IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems (TCAD), (early access), May 2018. [pdf]
  10. [INTE'17] R. Ewetz and C-K. Koh, "Fast Clock Scheduling and an Application to Clock Tree Synthesis", in Integration, the VLSI Journal, 56:115-127, January 2017. [pdf]
  11. [TODAES'16] R. Ewetz and C-K. Koh, "Construction of Reconfigurable Clock Trees for MCMM Designs using Mode Separation and Scenario Compression", in ACM Trans. on Design Automation of Electronic Systems (ACM), 21(4):57-83, June 2016. [pdf]
  12. [TCAD'15] R. Ewetz and C-K. Koh., “Cost-Effective Robustness in Clock Networks Using Near-Tree Structures”, in IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems (TCAD), 34(4):515-528, January 2015. [pdf]


CONFERENCE PUBLICATIONS
 
  1. [ASP-DAC'23] M. Rashed, SK Jha, and R. Ewetz, "Discovering the In-Memory Kernels of 3D Dot-Product Engines”, Asia and South Pacific Design Automation Conference (ASP-DAC), 2023.
  2. [ASP-DAC'23] S. Thijssen, SK Jha, and R. Ewetz, "FLOW-3D: Flow-Based Computing on 3D Nanoscale Crossbars with Minimal Semiperimeter”, Asia and South Pacific Design Automation Conference (ASP-DAC) , 2023.
  3. [TSRML'22] SK Jha, R. Ewetz, A. Velasquez, S. Jha, "Socially Responsible Reasoning with Large Language Models and The Impact of Proper Nouns”, Workshop on Trustworthy and Socially Responsible Machine Learning at Conference on Neural Information Processing (TSRML at NeurIPS), 2022.
  4. [ICCD'22] S. Thijssen, SK Jha, and R. Ewetz, "Equivalence Checking for Flow-based In-Memory Computing”, International Conference on Computer Design (ICCD), 2022.
  5. [ICCAD'22] M. Rashed, SK Jha, and R. Ewetz, "Logic Synthesis for Digital In-Memory Computing”, International Conference on Computer-Aided Design (ICCAD), 2022. (Best Paper Candidate) [pdf]
  6. [AICAS'22] S. Singireddy, R. Ewetz, SK Jha,"Deep Learning Toolkit-Driven Equivalence Checking of Flow-Based Computing Systems”, International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2022.
  7. [IJCAI-ECAI'22] SK. Jha, R. Ewetz , A. Velasquez, L. Pullum and S. Jha, "ExplainIt! A Tool for Computing Robust Attributions of Deep Neural Networks”, International Joint Conference on Artificial Intelligence (IJCAI), Demo Track, 2022.
  8. [DAC'22] S. Thijssen, SK Jha, and R. Ewetz, "PATH: Evaluation of Boolean Logic using Path-based In-Memory Computing”, Design Automation Conference (DAC), 2022. (Publicity Paper)
  9. [DAC'22] M. Rashed, Amro Awad, SK Jha, and R. Ewetz, "Towards Resilient Analog In-Memory Deep Learning via Data Layout Re-Organization”, Design Automation Conference (DAC), 2022. (Publicity Paper)
  10. [AAAI'22] S. Jha, R. Ewetz, A. Velasques, A. Ramanathan and S. Jha, "Shaping Noise for Robust Attributions in Neural Stochastic Differential Equations”, International Conference on Artificial Intelligence (AAAI), 2022.
  11. [DATE'22] M. Rashed, F. Yao. SK Jha, and R. Ewetz, "Hybrid Digial-Digital In-Memory Computing”, Design Automation and Test in Europe Conference (DATE), 2022.
  12. [ASP-DAC'22] M. Rashed, S. Thijssen, F. Yao. SK Jha, and R. Ewetz, "STREAM: Towards READ-based In-Memory Computing for Streaming based Data Processing”, Asia and South Pacific Design Automation Conference (ASP-DAC), 2022.
  13. [SECON'22] A. Michel and R. Ewetz, "Gradient-Based Adversarial Attack Detection via Deep Feature Extraction”, ”, SoutheastCon (SECON), 2022.
  14. [ICMLA'22] Kamalakkannan Ravi, Rickard Ewetz, and Adan Vela, "Classifying the Ideological Orientation of User-Submitted Texts in Social Media”, ”, International Conference on Machine Learning and Applications (ICMLA), 2022.
  15. [QIP'22] S. Ahmed, R. Ewetz, and G. Sukthankar, "Minimizing Elementary Gates in IBM Quantum Architectures using Deferred Swap Embedding”, Poster track, Conference on Quantum Information Processing (QIP), 2022.
  16. [MICRO'21] M. Chowdhuryy, M. Rashed, A. Awad, R. Ewetz, and F. Yao, "LADDER: Architecting Content and Location-aware Writes for Crossbar Resistive Memories”, International Symposium on Microarchitecture (MICRO), 2021.
  17. [ICCAD'21] M. Rashed, SK Jha, and R. Ewetz, "Hybrid Anlog-Digital In-Memory Computing”, International Conference On Computer Aided Design (ICCAD), 2021.
  18. [ICCAD'21] N. Uysal and R. Ewetz, "An OCV-Aware Clock Tree Synthesis Methodology”, International Conference On Computer Aided Design (ICCAD), 2021.
  19. [SEED'21] M. Chowdhuryy, Rickard Ewetz, Amro Awad and Fan Yao, "R-SAW: New Side Channels Exploiting Read Asymmetry in MLC Phase Change Memories”, International Symposium on Secure and Private Execution Environment Design (2021) , 2021.
  20. [GLSVLSI'21] S. Channamadhavuni, S. Thijssen, S. Jha, and R. Ewetz, "Accelerating AI Applications using Analog In-Memory Computing: Challenges and Opportunities”, Great Lakes Symposium on VLSI (GLSVLSI), 2021. (invited)
  21. [IJCAI'21] S. Jha, R. Ewetz, A. Velasques, and S. Jha, "On Smoother Attributions using Neural Stochastic Differential Equations”, International Joint Conference on Artificial Intelligence (IJCAI), 2021.
  22. [DAC'21] B. Zhang and R. Ewetz, "Towards Resilient Deployment of High Throughput In-Memory Neural Networks”, Design Automation Conference (DAC), 2021.
  23. [ISCAS'21] A. Velasquez, S.K. Jha, R. Ewetz and S. Jha, "Automated Synthesis of Quantum Circuits Using Symbolic Abstractions and Decision Procedures”, International Symposium on Circuits & Systems (ISCAS), 2021.
  24. [DATE'21] S. Thijssen, SK. Jha, and R. Ewetz, "COMPACT: Flow-Based Computing on Nanoscale Crossbars with Minimal Semiperimeter”, Design Automation and Test in Europe Conference (DATE), Feburary 2021. (Best Paper Candidate)
  25. [ICCAD'20] N. Uysal, B. Zhang, SK Jha, and R. Ewetz, "DP-MAP: Towards Resistive Dot-Product Engines with Improved Precision”, International Conference On Computer Aided Design (ICCAD), San Diego, 2020.
  26. [ISVLSI'20] B. Zhang, M. Murshed, F. Hussain, and R. Ewetz, "Fast Resilient-Aware Data Layout Organization for Resistive Computing Systems”, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Limassol, Cyprus, 2020.
  27. [GLSVLSI'20] B. Zhang, N. Uysal, D. Fan, and R. Ewetz, "Redundant Neurons and Shared Redundant Synapses for Robust Memristor-based DNNs with Reduced Overhead”, Great Lakes Symposium on VLSI (GLSVLSI), Beijing, China, 2020.
  28. [CVPRW'20] Steven Fernandes, Sunny Raj, Rickard Ewetz, Jodh Singh Pannu, Sumit Kumar Jha, Eddy Ortiz, Iustina Vintila, Margaret Salter, "Detecting Deepfake Videos Using Attribution-Based Confidence Metric”, Conference on Computer Vision and Pattern Recognition Workshops, May, 2020.
  29. [ISPD'20] N. Uysal, J. Cabrera, and R. Ewetz, "Synthesis of Clock Networks with a Mode Reconfigurable Topology and No Short Circuit Current”, International Symposium on Physical Design (ISPD), March 29- April 1, 2020, Taipei, Taiwan.
  30. [DATE'20] B. Zhang, N. Uysal, and R. Ewetz, "Computational Restructuring: Rethinking Image Processing using Memristor Crossbar Arrays”, Design Automation and Test in Europe Conference (DATE), March 2020.
  31. [ASP-DAC'20] B. Zhang, N. Uysal, D. Fan, and R. Ewetz, "Representable Matrices: Enabling High Accuracy Analog Computation for Inference of DNNs using Memristors”, Asia and South Pacific Design Automation Conference (ASP-DAC), 2020.
  32. [DAC'19] Z. He, J. Lin, R. Ewetz, J.-S. Yuan and D. Fan, "Noise Injection Adaption: End-to-End ReRAM Crossbar Non-ideal Effect Adaption for Neural Network Mapping”, Design Automation Conference (DAC), Las Vegas, NV, June 2-6, 2019.
  33. [GLSVLSI'19] B. Zhang, N. Uysal, and R. Ewetz, "STAT: Mean and Variance Characterization for Robust Inference of DNNs on Memristor-based Platforms”, Great Lakes Symposium on VLSI (GVLSI), Tysons Corner, VA, May. 9-11, 2019.
  34. [ASP-DAC'19] N. Uysal, W.-H. Liu, and R. Ewetz, "Latency Constraint Guided Buffer Sizing and Layer Assignment for Clock Trees with Useful Skew”, Asia and South Pacific Design Automation Conference (ASP-DAC), Japan, Jan. 21-24, 2019.
  35. [ASP-DAC'19] B. Zhang, N. Uysal, D. Fan, and R. Ewetz, "Handling Stuck-at-faults in Memristor Crossbar Arrays using Matrix Transformations”, Asia and South Pacific Design Automation Conference (ASP-DAC), Japan, Jan. 21-24, 2019. (Best Paper Candidate)
  36. [ICCD'18] B. Zhang and R. Ewetz, "Software and Hardware Techniques for Reducing the Impact of Quantization Errors in Memristor Crossbar Arrays”, International Conference on Computer Design (ICCD), Orlando, Oct. 7-10, 2018.
  37. [ASP-DAC'18] N. Uysal and R. Ewetz, "OCV Guided Clock Tree Topology Reconstruction”, Asia and South Pacific Design Automation Conference (ASP-DAC), Korea, Jan. 22-25, 2018.
  38. [ASP-DAC'18] C. Tan, R. Ewetz, and C-K. Koh, "Clustering of Flip-Flops for Useful-Skew Clock Tree Synthesis”, Asia and South Pacific Design Automation Conference (ASP-DAC), Korea, Jan. 22-25, 2018.
  39. [DAC'17] R. Ewetz, “A Clock Tree Optimization Framework with Predictable Timing Quality”, Design Automation Conference (DAC), Austin, TX, June. 19-22, 2017.
  40. [ISPD'17] R. Ewetz and C-K. Koh, “Clock Tree Construction based on Arrival Time Constraints”, International Symposium on Physical Design (ISPD), Portland, OR, March. 19-22, 2017.
  41. [ASP-DAC'17] S. Han, W.-H Liu, R. Ewetz, C.-K Koh, K.-Y Chao, and T.-C Wang, “Delay-driven Layer Assignment for Advanced Technology Nodes”, Asia and South Pacific Design Automation Conference (ASP-DAC), 2017.
  42. [ISPD'16] R. Ewetz, C. Tan, and C-K. Koh, “Construction of Latency-Bounded Clock Trees”, International Symposium on Physical Design (ISPD), Santa Rosa, CA, Apr. 3-6, 2016. [pdf]
  43. [ASP-DAC'16] R. Ewetz and C-K. Koh, “MCMM Clock Tree Optimization based on Slack Redistribution Using a Reduced Slack Graph”, Asia and South Pacific Design Automation Conference (ASP-DAC), Macau, Macau, Jan. 25-28, 2016. [pdf]
  44. [DAC'15] R. Ewetz, S. Janarthanan, and C-K. Koh, “Construction of Reconfigurable Clock Trees for MCMM Designs”, Design Automation Conference (DAC), San Francisco, CA, Jun. 7-11, 2015. [pdf]
  45. [ISPD'15] R. Ewetz and C-K. Koh, “Useful Skew Tree Framework for Inserting Large Safety Margins”, International Symposium on Physical Design (ISPD), Monterey, CA, Mar. 7- Apr. 1, 2015. [pdf]
  46. [ASP-DAC'15] R Ewetz, S. Janarthanan, and C.-K Koh., “Fast Clock Skew Scheduling based on Sparse-Graph Algorithms”, Asia and South Pacific Design Automation Conference (ASP-DAC), Chiba/Tokyo, Japan, Jan. 25-28, 2015. [pdf]
  47. [GLS-VLSI'14] R. Ewetz, A. Udupa G. Subbarayan, and C.-Kok Koh., “A TSV-cross-link-based approach to 3D-Clock Network Synthesis for Improved Robustness”, ACM Great Lakes Symposium on VLSI (GLS-VLSI), Huston, US, May 21-23, 2014. [pdf]
  48. [GLS-VLSI'14] R. Ewetz, W.-H Liu, K.-Y Chao, T.-C Wang, and C.-K Koh., “A Study on the use of Parallel Wiring Techniques for Sub-20nm Designs”, ACM Great Lakes Symposium on VLSI (GLS-VLSI), Huston, US, May 21-23, 2014. [pdf]
  49. [ISPD'13] R. Ewetz and C.-K Koh., “Local Merges for Effective Redundancy in Clock Networks”, International Symposium on Physical Design (ISPD), Lake Tahoe, US, Jun. 24-27, 2013. [pdf]


University of Central Florida