AREAS OF INTEREST
Topic 1: Emerging Computing Paradigms and Future Computing Systems
With the increasing amount of available digital data, computer vision, data analytics, and deep learning applications have emerged. Unfortunately, today's computing systems based on CMOS technology and von-Neumann architecture and unable to efficiently accelerate data intensive applications. Mainly, due to the bandwidth limited and power hungry data movement within the von-Neumann architecture. This research direction aims to design future computing systems using emerging devices and computing paradigms. We focus on technologies such as non-volatile memory (memristors, ReRAM, PCM, STT-MRAM, FeFET) and quantum (q-bits). The objective is to optimize metrics such as power, area, and robustness.

• [ICCAD'22] M. Rashed, SK Jha, and R. Ewetz, "Logic Synthesis for Digital In-Memory Computing”, International Conference on Computer-Aided Design (ICCAD), 2022. (Best Paper Candidate)
• [DAC'22] S. Thijssen, SK Jha, and R. Ewetz, "PATH: Evaluation of Boolean Logic using Path-based In-Memory Computing”, Design Automation Conference (DAC), 2022. (Publicity Paper)
• [DAC'22] M. Rashed, Amro Awad, SK Jha, and R. Ewetz, "Towards Resilient Analog In-Memory Deep Learning via Data Layout Re-Organization”, Design Automation Conference (DAC), 2022. (Publicity Paper)
• [DAC'21] B. Zhang and R. Ewetz, "Towards Resilient Deployment of High Throughput In-Memory Neural Networks”, Design Automation Conference (DAC), 2021.
• [DATE'21] S. Thijssen, SK. Jha, and R. Ewetz, "COMPACT: Flow-Based Computing on Nanoscale Crossbars with Minimal Semiperimeter”, Design Automation and Test in Europe Conference (DATE), Feburary 2021. (Best Paper Candidate)
• [ASP-DAC'19] B. Zhang, N. Uysal, D. Fan, and R. Ewetz, "Handling Stuck-at-faults in Memristor Crossbar Arrays using Matrix Transformations”, Asia and South Pacific Design Automation Conference (ASP-DAC), Japan, Jan. 21-24, 2019. (Best Paper Candidate)

Topic 2: Artificial Intelligence and Machine Learning
The growth and access to digital data and compute power has fueled the tremendous progress in artificial intelligence and machine learning over the past decade. Machine learning has surpassed human-level capabilities for many cognitive tasks. The group's research is focused on developing efficient, explainable, and robust artificial intelligence.

• [AAAI'22] S. Jha, R. Ewetz, A. Velasques, A. Ramanathan and S. Jha, "Shaping Noise for Robust Attributions in Neural Stochastic Differential Equations”, International Conference on Artificial Intelligence (AAAI), 2022.
• [IJCAI-ECAI'22] SK. Jha, R. Ewetz , A. Velasquez, L. Pullum and S. Jha, "ExplainIt! A Tool for Computing Robust Attributions of Deep Neural Networks”, International Joint Conference on Artificial Intelligence (IJCAI), Demo Track, 2022.
• [TSRML'22] SK Jha, R. Ewetz, A. Velasquez, S. Jha, "Socially Responsible Reasoning with Large Language Models and The Impact of Proper Nouns”, Workshop on Trustworthy and Socially Responsible Machine Learning at Conference on Neural Information Processing (TSRML at NeurIPS), 2022.
• [IJCAI'21] S. Jha, R. Ewetz, A. Velasques, and S. Jha, "On Smoother Attributions using Neural Stochastic Differential Equations”, International Joint Conference on Artificial Intelligence (IJCAI), 2021.
• [CVPRW'20] Steven Fernandes, Sunny Raj, Rickard Ewetz, Jodh Singh Pannu, Sumit Kumar Jha, Eddy Ortiz, Iustina Vintila, Margaret Salter, "Detecting Deepfake Videos Using Attribution-Based Confidence Metric”, Conference on Computer Vision and Pattern Recognition Workshops, May, 2020.

Topic 3: Computer-Aided Design for VLSI Circuits
Computer-aided design is used to automatically convert a design specification into a circuit consisting of billions of tranistors. The objective is to optimize performance metrics such as power, area, latency and throughput. The group's research has mainly been focused on synthesizing the clock networks that synchronize sequential VLSI circuits.

• [ICCAD'21] N. Uysal and R. Ewetz, "An OCV-Aware Clock Tree Synthesis Methodology”, International Conference On Computer Aided Design (ICCAD), 2021.
• [ISPD'20] N. Uysal, J. Cabrera, and R. Ewetz, "Synthesis of Clock Networks with a Mode Reconfigurable Topology and No Short Circuit Current”, International Symposium on Physical Design (ISPD), March 29- April 1, 2020, Taipei, Taiwan.
• [ASP-DAC'18] C. Tan, R. Ewetz, and C-K. Koh, "Clustering of Flip-Flops for Useful-Skew Clock Tree Synthesis”, Asia and South Pacific Design Automation Conference (ASP-DAC), Korea, Jan. 22-25, 2018.
• [DAC'17] R. Ewetz, “A Clock Tree Optimization Framework with Predictable Timing Quality”, Design Automation Conference (DAC), Austin, TX, June. 19-22, 2017.
• [DAC'15] R. Ewetz, S. Janarthanan, and C-K. Koh, “Construction of Reconfigurable Clock Trees for MCMM Designs”, Design Automation Conference (DAC), San Francisco, CA, Jun. 7-11, 2015. [pdf]